The process of creating an application-specific integrated circuit (ASIC) is commonly described in terms of a sequence of stages. In a commercial business setting in which ASICs are designed, stages commonly overlap each other in time, with different groups of design personnel simultaneously performing different tasks relating to the same end-product ASIC. The stages are known by various names but commonly include activities along the following lines.
At an early stage in the process, design personnel generate a description of the ASIC either in a hardware description language (HDL) or in a graphical schematic diagram form. An HDL description is commonly referred to as a register transfer level (RTL) design. This stage is followed by a stage in which simulations or other tests are performed upon the RTL design to verify that it performs the functions the designers intended. A later stage follows in which the RTL design is compiled or transformed into a netlist. A netlist is a collection of constructs commonly referred to as standard logic cells along with the interconnections between them. An ASIC fabricator commonly provides the designers with a library of standard logic cells that the ASIC fabricator has proven capable of transforming into physical structures on a semiconductor chip. Standard logic cells are commonly grouped or partitioned into “blocks.” For example, a complete memory subsystem might be designated as a block. Then, in a stage commonly referred to as “placement,” the standard logic cells or blocks are assigned locations on a region representing the chip.
The term “floorplan” is commonly used to refer to a tentative placement or arrangement of logic cells or partitioned blocks. In a related stage, commonly referred to as “routing,” locations on the chip for the signal paths that interconnect the blocks or cells are assigned. The logic of each block may be individually placed and routed, independently of the other blocks. In addition, at the top-level of the chip design, the blocks may be placed and the interconnections between them routed.
The result of the routing stage is a data file or database that includes the information needed by the fabricator to fabricate or produce the actual semiconductor chip. The information represents the photolithographic masks that are used in the fabrication process. However, additional verification, analysis and optimization stages are commonly performed prior to finalizing the data file and fabricating the chip.
Each of the above-described stages involves the use of one or more automated design tools, i.e., computer software. For example, a floorplanning tool commonly receives as its input a netlist describing all of the blocks, the standard logic cells within the blocks, and their interconnections. A person can use the floorplanning tool to place or arrange the blocks at locations within the region representing the chip, setting aside spaces to accommodate the interconnects between blocks in a top-level routing stage. The data set that represents the output of a tool used in one stage commonly represents the input of another tool used in the next stage.
A chip design is hierarchical in the sense that it consists of a block-level design or data set describing each block as well as a top-level design or data set for the chip as a whole that describes the locations of the blocks and the interconnections between blocks. The set of block designs plus the top-level design in accordance with the floorplan is reflected in what is sometimes referred to as a full-chip data set or database. The final stage in the process of designing each block involves verifying that the design functions in the intended manner. The final stage in the process of designing the chip as a whole, after the stage in which all blocks have been placed, involves a top-level verification of the functionality of the chip. Verification tools exist for these purposes.
As in any design process, design personnel may desire to make changes to the chip design after it has been completed or at some point during the design process. Changes made later in the design process have a greater potential to delay completion of the chip design project because a change in one aspect of the chip has the potential to impact other aspects of the chip. The potential for delaying the design project arises because it is often difficult to determine how a change in one aspect of the chip might impact other aspects of the chip. For example, a change that design personnel may make to one block or to interconnections between blocks has the potential to lead the automated design tool involved in a later or related stage of the overall design process to automatically change some other aspect of the design, such as power distribution interconnections, clock signal distribution interconnections, ports (i.e., the boundaries defining signal inputs and outputs of blocks), top-level feed-throughs (i.e., interconnections that pass signals around a block), or other aspects. For example, even a change that is wholly within a block has the potential to affect the top-level interconnection routing if the change increases the size of the block to an extent that interconnections must be rerouted or moved. Such changes generally imply a change in the floorplan.
A change in one aspect of the chip design has the potential to impact other aspects of the chip design to an extent severe enough that the result of the above-referenced top-level verification stage may be that the verification fails. A failure of the design to verify at the top level means that a chip reflecting that design may not perform as intended if it were fabricated. At least two alternative methods are known for handling this potential problem.
A first method is to perform all of the above-referenced stages of the design process again, substituting the changed item (e.g., block, interconnection, port, etc.) for that of the original design. The netlist is then input to the floorplanning tool, which processes the netlist and outputs a new floorplan data set. The floorplan may be partitioned into blocks. The blocks are then provided as input to the block-level place-and-route tool and the top-level place-and-route tool, even though many of the blocks may be unchanged. It can be noted that many of the partitioned blocks may be identical to the blocks in the original design if the change affected only a small number of blocks. Then, the output of the place-and-route tool is input to the full-chip verification tool, which verifies the chip design as a whole. As all of the stages of the process have been performed again, there is no inherent reason why the top-level verification should fail if it such verification of the original design (i.e., before the change was made) previously passed. This first method is thus a conservative approach. The drawback of this approach, however, is the delay caused by re-doing all of the steps and sub-steps of the design process. The later in the design process, i.e., the more blocks that have already been completed at the time of the change, the greater the potential delay to the chip design project as a whole.
A second, less conservative, method is to simply substitute the changed item for the original item in the overall chip design and proceed directly to the full-chip verification stage. If the full chip design passes verification, the design can proceed to fabrication. But if the full-chip verification fails, then design personnel must generally re-do all of the steps as in the first method. Thus, this second method risks delaying the chip design project even more.
Experienced chip design personnel often can correctly predict whether a change in one aspect of a chip design is likely to impact other aspects to an extent that the top-level verification would fail. A change that is made wholly within a block often has no significant impact on other blocks, interconnections between blocks, ports, or other aspects of the chip design. However, there is no known method by which such predictions can be rigorously tested.